The present invention relates to a system for controlling an internally-installed cache memory to maintain consistency between a main memory and an internally-installed cache in a data processing apparatus and for internally-installing the cache into which the data in the main memory is copied.
To meet recent demand for a high-speed data-processing apparatus, the data access to the main memory must be speeded up. Therefore, a cache memory for copying data from the main memory is provided in the data processing apparatus and the cache is made larger.
To raise the performance of the apparatus, increased use has been made of a multi-processor structure with a plurality of micro-processors (MPUs) instead of a single micro-processor, and of a system in which a DMA controller is used to speed up transmission speed between memories.
Where a system with such a structure has a cache memory installed in an MPU/CPU, it is nonsense that data of the main memory in which the content has already been changed because another processor has written data in the main memory is maintained in the internally-installed cache memory. Thus, it is necessary to maintain consistency between the internally-installed cache memory and the main memory.
To maintain consistency between the internally-installed cache memory and the main memory, a function called an address monitor is conventionally used. This address monitor observes the system bus to which the main memory is connected. When the other bus master produces a write signal for the main memory, the address monitor reads the address on the system bus and compares it with the content in the tag portion of the internally-installed cache memory. When the address accords with the content in the tag portion, the corresponding data in the internally-installed cache memory is invalidated. Thus, consistency is maintained between the main memory and the internally-installed cache memory.
As an ordinary program is written using a logic address, it is necessary to translate the logic address to a physical address so that the program can be operated on an actual hardware. This operation is called an address translation.
The offset portion of the logical address subjected to this address translation is not changed in the physical address and the portion other than the offset portion is not the same as that of the physical address when the logical address is translated to the physical address according to the address translation table.
As the internally-installed cache is small in the conventional data processing apparatus, only the offset portion of the logical address is used as a set address, thereby forming an N-way set associative cache. In this case, the offset portions of the logical address and the physical address are the same, even if they are subjected to address translation. Therefore, the physical address output on the system bus is directly used to determine a set address of cache to be subjected to a comparison and to access the set address of the cache in which the content corresponding to the physical address is stored.
Where, in accordance with a request for a larger cache memory, the cache is made larger, the offset portion is insufficient for the set address. A bit position for which the logical address may be different from the physical address is used.
When the physical address of the system bus is used as the set address of the cache, there is no problem when the logical address is the same as the physical address. When the logical address is different from the physical address, the conventional control invalidates a different content of the cache memory and the portion of the cache memory which should be invalidated remains valid.
Views showing the state of the cache, shown in FIG. 1A, 1B and 1C, are explained. In the following explanation, LA represents a logical address and PA represents a physical address. LA(a:b) represents a bit series from the a-th bit to the b-th bit of the logical address. PA(a:b) represents a bit series from the a-th bit to the b-th bit of the physical address. In this example, both the logical address and the physical address comprise 32 bits. The highest bit is the 31st bit and the lowest bit is 0th bit.
The address translation table shown in FIG. 1A is provided and correspondence between the address and the data is as shown in FIG. 1B. The data is registered in the cache as shown in FIG. 1C in which the tag portion and the cache memory portion are shown.
When PA(31:1)=H'00003000 is provided on a system bus as an address to be address-monitored, and PA(14:4)=H'300 is a set address, PA(31:12)=H'0003 on the system bus is compared with H'0002 stored in the set address H'300 in the tag portion and as they do not coincide, the data stored in the set address H'300 is not subjected to any operation. PA(31:1)=H'00003000, which should be originally invalidated, remains.
When the portion of the logical address other than the offset portion is used as the set address of the cache, the physical address cannot determine the set address to be subjected to the address comparison.
Therefore, where the portion of the logical address other than the offset portion is used as the set address of the cache of the set associative structure, the conventional method cannot maintain consistency between the main memory and the internally-installed cache.